Scan testing transforms the test of a sequential circuit into a combinatorial test problem. In conjunction with automated test pattern generation (ATPG) software, this allows to handle the ever increasing complexity of digital designs. However, test data volume continues to grow with the design's complexity. Moreover, new process technologies and materials which allow smaller feature sizes require more comprehensive tests covering a range of different fault models [1]. Today, test cost constitutes a significant part of the production cost, typically in the range of 10-20% [2].
To keep test time and automated test equipment's (ATE) memory requirements in check, test input stimuli as well as test response data are transferred in compressed form. The basic design of scan test with test compression is depicted in FIG. 1. With test compression, the ATE transfers compressed test stimuli to the device-under-test (DUT), where it is deflated by a decompressor circuitry. The scan-out data is likewise compacted by an on-chip compactor. This setup allows to feed a large number of short internal scan chains with only a limited number of external ATE channels. This is advantageous as a large number of (relatively) short scan chains reduces the number of scan shift cycles per pattern, thus reducing test time and test cost.
A major obstacle to efficient test response compaction are unknown values (x-values) captured by scan cells during test. If test responses with x-values are compacted, some of the outputs of the compactor may also take unknown values and the correctness of the compactor inputs cannot be verified at the compactor outputs. The presence of x-values hence reduces observability of (non-x) scan cells which may lead to reduced test quality and/or limited compaction rates.
To overcome these problems a number of ideas have been proposed. Some compactors are designed to tolerate a limited number of x-values, e.g. [3], [4], [5], [6], [7], [8]. In general, however, these solutions are only applicable to designs with very low x-densities. A slightly different approach is taken in [9], [10], where scan out data is rearranged to reduce x-value impact before it is fed into the compactor.
A second approach is to mask the x-values before they enter the compactor [11], [12], [13], [14], [15]. These compactors require the transfer of additional masking data to the DUT. Furthermore, these concepts usually entail over-masking, i.e. the overall observability of scan cells is decreased. This may result in a lower probability to detect non-targeted faults.
Thirdly, output selection may be used to circumvent x-values [16], [17], [18]. Recently, the use of ATE timing flexibility to observe a subset of the output values of an accelerated compactor has been proposed [19], [20].
To further reduce test cost, circuits may be tested in parallel (multi-site testing). In that case, a number of DUTs shares the same input signals while transferring their test responses on separate channels each.
Furthermore, diagnosis data from volume testing is increasingly used for yield learning [21]. Hence, test compaction should also allow for efficient diagnosis. It has been demonstrated that test output data compacted into a single, 1-bit-wide output stream by an XOR-tree can be efficiently used for fault detection and diagnosis [22], [23]. However, these works considered x-free circuits only.